Stuffing process for reducing waiting time jitter and device for executing the process

ABSTRACT

A stuffing process and device for reducing waiting time jitter by: determining the mean loading of an elastic memory as precisely as possible; determining a loading error constituted by a difference between an actual value and a set value of the mean loading; producing a sum of successive loading errors; and determining the manner in which stuffing is to take place in order to keep the error sum as constant as possible.

BACKGROUND OF THE INVENTION

The present invention relates to a stuffing process and apparatus forreducing waiting time jitter, of the type in which:

a first digital signal (A) with a first bit rate is supplied to asynchronizer and the first digital signal is written into an elasticmemory (ES) in the synchronizer with a first clock pulse (t_(A)) havinga pulse rate which corresponds to the first bit rate of the firstdigital signal (A);

b. a second digital signal (B) is read out of the elastic memory (ES) ata second bit rate with a second clock pulse (t_(B)) having a pulse ratewhich corresponds to the second bit rate of the second digital signal(B), whereby the elastic memory (ES) will have a mean loading; and

c. in a frame counter (RZ), stuffing frames of the second digital signal(B) are generated, reading out of the elastic memory is controlled, andstuffing is performed as a function of a control parameter supplied tothe frame counter.

If a first asynchronous digital signal is intended to be inserted into asecond digital signal, the basic problem of frequency adaption arises.This problem is solved by stuffing. A problem of the conventionalstuffing process lies in that the first digital signal recovered bydestuffing may contain a low-frequency jitter, waiting time jitter,which can no longer be removed. The size of this jitter is the result ofthe stuffing process employed.

The conventional process for positive stuffing and the size of waitingtime jitter caused by this is known from D. L. Duttweiler, in "WaitingTime Jitter", The BELL system Technical Journal, Vol. 51, No. 1, 1972,pages 165 to 207. Waiting time jitter in the course ofpositive-null-negative-null stuffing is treated in an article by F.Kuhne, K. Lang, in "Positiv-Null-Negativ-Stopftechnik furMultiplexubertragung plesiochroner Datensignale" [Positive-Null-NegativeStuffing Technology for Multiplex Transmission of Plesiochronous DataSignals], Frequenz [Frequency], Vol. 32, No. 10, 1978, pages 281 to 287.

It is known from this reference to supply a first digital signal with afirst bit rate to a synchronizer and to write it there with a firstpulse corresponding to the bit rate of the first digital signal into anelastic memory. A second digital signal is read out of the memory with asecond pulse, the second clock rate corresponding to the bit rate of thesecond digital signal. The frame of the second digital signal isgenerated and the read activation of the elastic memory is controlled incounters. The mean loading of the elastic memory is determined once perframe of the second digital signal. A difference between the meanloading and the set value for the mean loading is formed for eachstuffing frame of the second digital signal. It is known to compare thedifference with a maximum deviation. If the difference is greater thanthe maximum deviation, stuffing is performed.

A process for reducing waiting time jitter in the course ofpositive-null-negative stuffing was described by D. CHOI in "WaitingTime Jitter Reduction", IEEE Transactions on Communications, Vol. 37,No. 11, 1989, pages 1231 to 1236. The author assumes that a nominalstuffing process from null, such as is the case in the positive-negativestuffing process, results in large waiting time jitter. Therefore, theproposed process initiates a stuffing ratio not equal to null and inthis way achieves a reduction of waiting time jitter.

In the publication by W. D. Grover, T. E. Moore, J. A. McEachern in"Waiting Time Jitter Reduction by Synchronizer Stuff ThresholdModulation", GLOBECOM '87, pages 514 to 518, additional stuffingoperations are provided for reducing waiting time jitter, whichadditional stuffing operations take place in such sequence that theeffect is a frequency displacement of the jitter. It is only requiredfor executing this process to provide a new control in the synchronizerfor the time when stuffing is intended. While up to now stuffing wasalways performed when constant thresholds were exceeded in eitherdirection, the thresholds are modulated in the present case.

This species-defining reference therefore proceeds from a methodcorresponding to that in the article by Kuhne and Lang. However, themethod does not operate with fixed thresholds, instead, the thresholdsare modulated.

The processes for reducing waiting time jitters described in thesearticles each have a free parameter, by means of which waiting timejitter is defined (for example the length of the periods in the case ofthreshold modulation). However, it is not permissible to choose thisparameter in such a way that the smallest possible waiting time jitterresults. Instead, the critical frequency of the PLL circuit of thedesynchronizer must be taken into consideration. The larger thiscritical frequency, the more waiting time jitter must be allowed bymeans of the choice of the free parameter. If this is not taken intoaccount, an additional jitter component is superimposed on the pulsegenerated by the desynchronizer, which is greater than the waiting timejitter.

There is a necessity of adapting the synchronizer and the desynchronizerstructurally to each other on account of the free parameter. If thecritical frequency of the PLL circuit is greater than expected, therewill be increased jitter of the recovered pulse. But if in contrast tothis the critical frequency of the PLL circuit is smaller than expected,this jitter is only negligibly reduced, because in this case waitingtime jitter is dominant.

SUMMARY OF THE INVENTION

It is the object of the invention to recite a process by means of whichwaiting time jitter can be reduced with the use of arbitrary customarydesynchronizers, and to recite a device by means of which this processcalm be executed.

The objects according to the invention are achieved by an improvement inthe method described at the beginning of this specification, whichimprovement includes the steps of:

determining the mean loading of the elastic memory (ES) at a rate ofonce per stuffing frame of the second digital signal (B);

producing an indication of a difference between the mean loading and aselected loading value for each stuffing frame of the second digitalsignal (B);

deriving a sum of the difference indicated during an existing stuffingframe and all previous stuffing frames for which the steps ofdetermining and producing were performed;

deriving, from the difference indicated during an existing stuffingframe and the current sum, an estimated sum value for the next occurringstuffing frame on the assumption that stuffing will not be performedduring the next occurring stuffing frame;

comparing the estimated sum value with at least one threshold value anddetermining, as a function of this comparison, a control parameter valuewhich can control stuffing in a manner such that the sum derived in thefirst-recited deriving step remains at least approximately constant; and

supplying the value determined in the comparing step as the controlvalue, to the frame counter (RZ).

The objects according to the invention are further achieved, in a deviceof the type described earlier herein by the improvement wherein suchdevice further includes:

means for determining the mean loading of the elastic memory (ES) at arate of once per stuffing frame of the second digital signal (B);

means for producing an indication of a difference between the meanloading and a selected loading value for each stuffing frame of thesecond digital signal (B);

means for deriving a sum of the difference indicated during an existingstuffing frame and all previous stuffing frames for which a mean loadingwas previously determined and an indication of a difference waspreviously produced;

means for deriving, from the difference indicated during an existingstuffing frame and the current sum, an estimated sum value for the nextoccurring stuffing frame on the assumption that stuffing will not beperformed during the next occurring stuffing frame;

means for comparing a currently derived estimated sum value with atleast one threshold value and for determining, as a function of thiscomparison, a control parameter value which can control stuffing in amanner such that the sum derived by the means for deriving remains atleast approximately constant; and

means for supplying the value determined by the means for comparing, asthe control value, to the frame counter (RZ).

By means of the stuffing process in accordance with the invention, afirst digital system is inserted into a second digital signal in such away, that the first digital signal can be recovered arbitrarily free ofjitter. A further advantage is that standardized frames can be employedfor the second digital signal. In accordance with the invention, acustomary process and thus a customary desynchronizer can be used fordestuffing. The properties of the stuffing process mentioned areattained by deformation of the spectrum of the stuffing jitter. In thiscase the proportion of time low frequencies of the stuffing jittershould be small, because these components cannot be filtered out by thePLL arrangements contained in the desynchronizers.

To achieve by means of the stuffing process in accordance with theinvention that the first digital signal can be recovered arbitrarilyfree of jitter, it is necessary to be able to determine loading of theelastic memory as accurately as possible during stuffing.

A possibility of determining loading as exactly as possible is recitedin one of the exemplary embodiments.

The stuffing process in accordance with the invention is characterizedby the following features: the following process steps are performed ineach stuffing frame of the second digital signal:

The mean loading of the elastic memory is determined as exactly aspossible. A difference between the ACTUAL value and the SET value of themean loading of the elastic memory is determined. This differencerepresents the loading error. The loading error is added up, i.e. anerror sum is formed. The decision as to how or whether stuffing takesplace is made in view of the attempt to keep the error sum as constantas possible.

Reasons will be given below why it is important to keep the error sum asconstant as possible. In the recovery of the original digital signal,the associated pulse is present in a strongly jittered form. It iscustomary to filter out the high-frequency portions of this jitter inthe desynchronizer, for example with a PLL circuit, for the stuffingframes of the second digital signal B. The transmission function of thefilter can be compared approximately with that of an integrator, wherethe integrator forms the integral of the loading error. Because theerror sum is also to be considered an approximation for the integral ofthe loading error, there is an approximate proportional connectionbetween the time characteristic of the error sum and the timecharacteristic of the jitter of the filtered pulse of the recoveredoriginal digital signal.

The critical frequency of the filter and the reciprocal stuffing framefrequency of the second digital signal B enter into the proportionalityconstant. Thus, as constant as possible an error sum determines a phaseunchanged in time, a reduction of the critical frequency of the filtersresults in a reduction of jitter.

BRIEF DESCRIPTION OF THE DRAWING

Exemplary embodiments of the invention will be described by means of thedrawings. Shown are in:

FIG. 1a synchronizer for positive stuffing, and

FIG. 2 a synchronizer for positive-null-negative stuffing.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a circuit which makes stuffing decisions during positivestuffing in such a way that the error sum remains as constant aspossible. A first digital signal A with a first bit rate correspondingto a first pulse t_(A) is supplied to the synchronizer. The outputsignal of the synchronizer is a second digital signal B with a secondbit rate corresponding to a second pulse t_(B). This second digitalsignal B is transmitted to a desynchronizer (not shown in the drawingfigure), in which the first digital signal A with the first bit rate isregenerated. The bit rates of the data signals A and B have beenselected to be such, that a transmission of the first digital signal Ain the second digital signal B is possible by means of pulse stuffingtechniques. The synchronizer has an elastic memory ES, to which thefirst digital signal A is supplied. It is written in with the pulset_(A). The second digital signal B is read out of the elastic memory ESwith the pulse t_(B). A frame counter RZ is provided for generating theframe of the second digital signal and controls the read activation ofthe elastic memory ES. The elastic memory ES signals by means of theactual loading af how many bits are in the memory at the time. Theactual loading af is increased by one bit when a bit is written into theelastic memory, when reading out a bit the actual loading af isdecreased by one bit. The integrator I forms the mean loading mf fromthe actual loading af. The mean loading mf is the integral of the actualloading af over a given window of time. The integrator I provides a newvalue for the mean loading mf for each frame of the digital signal B.The mean loading of the elastic memory ES is supplied to a time-discretenetwork ZN, which is clocked with the stuffing frame frequency of thesecond digital signal B. First, the mean loading mf is compared with theSET value of the mean loading mf in this time-discrete network ZN. Theloading error ff is determined in this way. The sum of the loadingerrors ff of all previous stuffing frames, the previous error sum fs, isavailable. The error sum of the instantaneous stuffing frame of thedigital signal B is formed from the loading error ff and the previouserror sum fs, ff+fs, in the time-discrete network ZN. An estimated valuefor the error sum in the next stuffing frame of the digital signal B,fs+2ff, is formed from this error sum of the instantaneous stuffingframe of the digital signal B and the loading error of the instantaneousdigital signal B. The estimated value for the next error sum fs+2ff issupplied to a circuit SE for making the stuffing decision. It is decidedin this circuit SE whether stuffing should take place. If the estimatedvalue of the error sum in the next frame lies above a threshold,stuffing will not be performed. However, if its lies below thisthreshold, positive stuffing takes place. The information as to whetherstuffing is performed is passed on by the circuit SE for making thestuffing decision to the frame counter RE.

A synchronizer for positive-null-negative stuffing is illustrated inFIG. 2. It differs from the synchronizer for positive stuffing by thedesign of the circuit SE for making the stuffing decision. Duringpositive-null-negative stuffing, the stuffing decision is also made inthis circuit in such a way, that the error sum remains as constant aspossible. The decision is made with the aid of a pair of thresholds, thethresholds of which are at distance of one bit. If the estimated valueof the error sum in the next stuffing frame of the digital signal B lieswithin a pair of thresholds, stuffing is not performed. However, if thevalue lies outside of the pair of thresholds, either positive ornegative stuffing is performed, depending on the deviation of theestimated value from the pair of thresholds.

In each case a stuffing ratio of zero is made the basis for forming theestimated value of the error sum of the next stuffing frame of thedigital signal B.

I claim:
 1. In a stuffing process for reducing waiting time jitter,which process includes the steps of:a. supplying a first digital signal(A) with a first bit rate to a synchronizer and writing the firstdigital signal into an elastic memory (ES) in the synchronizer with afirst clock pulse (t_(A)) having a pulse rate which corresponds to thefirst bit rate of the first digital signal (A); b. reading a seconddigital signal (B) at a second bit rate out of the elastic memory (ES)with a second clock pulse (t_(B)) having a pulse rate which correspondsto the second bit rate of the second digital signal (B), whereby theelastic memory (ES) will have a mean loading; and c. in a frame counter(RZ), generating stuffing frames of the second digital signal (B),controlling reading out of the elastic memory, and performing stuffingas a function of a control parameter supplied to the frame counter, theimprovement wherein said process further comprises: d. determining themean loading of the elastic memory (ES) at a rate of once per stuffingframe of the second digital signal (B); e. producing an indication of adifference between the mean loading and a selected loading value foreach stuffing frame of the second digital signal (B); f. deriving a sumof the difference indicated during an existing stuffing frame and allprevious stuffing frames for which said steps of determining andproducing were performed; g. deriving, from the difference indicatedduring an existing stuffing frame and the sum derived in step f, anestimated sum value for the next occurring stuffing frame on theassumption that stuffing will not be performed during the next occurringstuffing frame; h. comparing the estimated sum value with at least onethreshold value and determining, as a function of this comparison, acontrol parameter value which can control stuffing in a manner such thatthe sum derived in step f remains at least approximately constant; andi. supplying the value determined in step h, as the control value, tothe frame counter (RZ).
 2. A stuffing process in accordance with claim1, wherein the process includes positive stuffing, and during positivestuffing the estimated sum value is compared with a threshold andstuffing is always performed if the estimated value lies below thethreshold and is not performed if the estimated value lies above thethreshold.
 3. A stuffing process in accordance with claim 1, wherein theprocess includes positive-null-negative stuffing, and duringpositive-null-negative stuffing, the estimated sum value in the nextstuffing frame of the second digital signal (B) is compared with a pairof threshold values, and stuffing is performed if the estimated sumvalue lies outside of the range of values between the pair of thresholdvalues and is not performed if the estimated value lies within the rangeof values between the pair of threshold values.
 4. A device for carryingout the process in accordance with claim 1, comprising:a. an elasticmemory (ES) having a write input connected for writing in of the firstdigital signal (A) under control of the first clock pulse (t_(A)) havinga pulse rate which corresponds to the first bit rate of the firstdigital signal (A) and a read output connected for reading out thesecond digital signal (B) under control of the second clock pulse(t_(B)) having a pulse rate which corresponds to the second bit rate ofthe second digital signal (B), whereby the elastic memory (ES) will havea mean loading; and b. a frame counter (RZ) for generating stuffingframes of the second digital signal (B) at a stuffing frame frequency,controlling reading out of the elastic memory (ES) and performingstuffing as a function of a control parameter supplied to said framecounter, wherein said device further comprises: c. a circuit fordetermining the mean loading (I) of said elastic memory (ES) at leastonce per stuffing frame of the second digital signal (B); d. atime-discrete network (ZN) which is clocked at the stuffing framefrequency of the second digital signal (B) and to which the mean loadingis supplied, said time-discrete network (ZN) being operative todetermine a control parameter value which controls stuffing in such away that the sum of the differences between the mean loading and a setvalue for the mean loading, a respective one of which differences isformed for each stuffing frame of the second digital signal, remains atleast approximately constant for all stuffing frames of the seconddigital signal (B), and said time-discrete network (ZN) further beingoperative to determine, from the difference indicated during an existingstuffing frame and the current sum, an estimated sum value for the nextoccurring stuffing frame on the assumption that stuffing will not beperformed during the next occurring stuffing frame; e. a circuit (SE)connected to receive the estimated sum value and for performing thecomparing step, said circuit (SE) being operative for comparing theestimated value with at least one threshold and for determining, as afunction of this comparison, the control parameter value which cancontrol stuffing so that the sum of the differences remains at leastapproximately constant; and f. means connected for supplying thedetermined control parameter value to said frame counter (RZ).
 5. In astuffing device for reducing waiting time jitter, which deviceincludes:a. means for supplying a first digital signal (A) with a firstbit rate to a synchronizer and for writing the first digital signal intoan elastic memory (ES) in the synchronizer with a first clock pulse(t_(A)) having a pulse rate which corresponds to the first bit rate ofthe first digital signal (A); b. means for reading a second digitalsignal (B) at a second bit rate out of the elastic memory (ES) with asecond clock pulse (t_(B)) having a pulse rate which corresponds to thesecond bit rate of the second digital signal (B), whereby the elasticmemory (ES) will have a mean loading; and c. a frame counter (RZ)containing means for generating stuffing frames of the second digitalsignal (B), for controlling reading out of the elastic memory, and forperforming stuffing as a function of a control parameter supplied to theframe counter, the improvement wherein said device further comprises: d.means for determining the mean loading of the elastic memory (ES) at arate of once per stuffing frame of the second digital signal (B); e.means for producing an indication of a difference between the meanloading and a selected loading value for each stuffing frame of thesecond digital signal (B); f. means for deriving a sum of the differenceindicated during an existing stuffing frame and all previous stuffingframes for which a mean loading was previously determined and anindication of a difference was previously produced; g. means forderiving, from the difference indicated during an existing stuffingframe and the sum derived by said means for deriving a sum of thedifference, an estimated sum value for the next occurring stuffing frameon the assumption that stuffing will not be performed during the nextoccurring stuffing frame; h. means for comparing a currently derivedestimated sum value with at least one threshold value and fordetermining, as a function of this comparison, a control parameter valuewhich can control stuffing in a manner such that the sum derived by saidmeans for deriving remains at least approximately constant; and i. meansfor supplying the value determined by said means for comparing, as thecontrol value, to said frame counter (RZ).